Non-Patent Document 1 describes a pipelined analog-digital (A/D) converter. Non-Patent documents 2 to 5 and Patent Documents 1 to 4 describe cyclic analog-digital converters. A sample/hold (S/H) circuit is provided at the input of the cyclic analog-digital converter. The cyclic analog-digital converter includes two-stage circuit blocks connected in series. Non-Patent Document 6 describes background calibration. Furthermore, Patent Document 5 describes digital correction of capacity, and Patent Document 6 describes a pipelined A/D converter.
[Non-Patent Document 1] Yun Chin, “Inherently linear capacitor averaging techniques for pipelined A/D conversion,” IEEE Trans. Circuits and Systems-IIm, vol. 47, no. 3, pp. 229-232, 2000.
[Non-Patent Document 2] P. Quinn, M. Pribytko, “Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 um CMOS, “Proc. 2003 Custom Integrated Circuits Conf., pp. 425-428, 2003.
[Non-Patent Document 3] B. Ginetti, P. G. Jespers, A. Vandemeulebroecke, “A CMOS13-b cyclic RSD A/D converter”, IEEE J. Solid-State Circuits vol. 27, no. 7, pp. 957-965, 1992.
[Non-Patent Document 4] K. Nagaraj, “Efficient circuit configuration for algorithmic analog to digital converters, “IEEE Trans. Circuits and Systems II, vol. 40, no. 12, pp. 777-785, 1993.
[Non-Patent Document 5] H. S. Lee, “A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC,” IEEE J. Solid-State Circuits, vol. 29, No. 4, pp. 509-515, 1994.
[Patent Document 1] U.S. Pat. No. 5,027,116.
[Patent Document 2] U.S. Pat. No. 5,212,486.
[Non-Patent Document 6] J. Ming, S. H. Lewis, “An 8 b 80M Sample/s pipelined ADC with background calibration”, IEEE Int. Solid-State Circuits Conf., pp. 42-43, 2000.
[Patent Document 3] U.S. Pat. No. 5,027,116.
[Patent Document 4] U.S. Pat. No. 5,212,486.
[Patent Document 5] U.S. Pat. No. 5,510,789.
[Patent Document 6] Japanese Patent Application Laid-open No. 2006-33304.